View X9460KV14I_395068.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
X9460
Low Noise, Low Cost, High End Features, Dual Audio Log Potentiometer Data Sheet October 17, 2005 FN8203.2
Dual Audio Control Digitally Controlled Potentiometer (XDCPTM)
The X9460 integrates two digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The two XDCPs can be used as stereo gain controls in audio applications. Read/Write operations can directly access each channel independently or both channels simultaneously. Increment/Decrement can adjust each channel independently or both channels simultaneously. The X9460 contains a zero amplitude wiper switching circuit that delays wiper changes until the next zero crossing of the audio signal. The digitally controlled potentiometer is implemented using 31 polysilicon resistors in a log array. Between each of the resistors are tap points connected to the wiper terminal through switches. The XDCPs are designed to minimize wiper noise to avoid pops and clicks during audio volume transitions. The position of the wiper on the array is controlled by the user through the 2-wire serial bus interface. Power-up reset the wiper to the mute position.
Features
* Dual Audio Control - Two 32 Taps Log Pots * Zero Amplitude Wiper Switching * 2-Wire Serial Interface 4 Slave Byte Addresses for Writes[A1,A0] * Total Resistance: 33k Each XDCP (Typical) * Dual Voltage Operation V+/V- = 2.7 to 5.5V * Temp Range = -40C to +85C * Package Options 14 L d TSSOP * Zero Amplitude Wiper Switching * Pb-Free Plus Anneal Available (RoHS Compliant)
Audio Performance
* 0 to - 62dB Volume Control * -92dB Mute - Power-Up to Mute Position * SNR -96dB
Pinout
X9460 (14 LD TSSOP) TOP VIEW
SDA SCL VCC V+ VSS A0 A1 1 2 3 4 5 6 7 X9460 14 13 12 11 10 9 8 VRH-right RL-right RW-right RH-left RL-left RW-left
* THD+N: -95dB @1kHz * Crosstalk Rejection: -102dB @ 1kHz * Channel-to-Channel Variation: 0.1dB * 3dB-Cutoff: 100kHz
Applications
* Set Top Boxes * Stereo Amplifiers * DVD Players * Portable Audio Products
Ordering Information
PART NUMBER X9460KV14I* X9460KV14IZ* (Note) X9460KV14I-2.7* X9460KV14IZ-2.7* (Note) PART MARKING X9460KV I X9460KV Z I X9460KV G X9460KV Z G 2.7 to 5.5 VCC LIMITS (V) 5V 10% TEMP RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE 14 Ld TSSOP 14 Ld TSSOP (Pb-free) 14 Ld TSSOP 14 Ld TSSOP (Pb-free)
*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X9460 Simplified Functional Diagram
VCC Power-on Recall mute data address I2C bus BUS INTERFACE CONTROL & REGISTER select inc/dec
RH-Left
RH-Right
V+ 62dB total
STEP SIZE -1dB
POT Left POT Right
# OF STEPS 11 10 5 4 1
-2dB -3dB -4dB Mute
VSS
RW-Left
RL-Left
RW-Right
RL-Right
V-
Detailed Functional Diagram
VCC
V+
Power-on Recall mute SCL SDA A0 A1 INTERFACE AND CONTROL CIRCUITRY
WIPER COUNTER REGISTER (WCR) POT Left
RH-Left
RL-Left RW-Left RW-Right
8 D ATA WIPER COUNTER REGISTER (WCR) POT Right RH-Right
RL-Right
VSS
V-
2
FN8203.2 October 17, 2005
X9460 Typical Application
Audio Audio DAC X9460 2 XDCP Amplifier Left
Gain / Volume Control Left Channel Control Right Channel Control Simultaneous Left and Right Channel Control Power-up in Mute
Audio => RHL, RHR RWL, RWR => Amplifier Audio Amplifier Right
Controller
Serial Bus
EEPROM
Pin Assignments
PIN (TSSOP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYMBOL SDA SCL VCC V+ VSS A0 A1 RW-left RL-left RH-left RW-right RL-right RH-right VSerial Data Serial Clock System Supply Voltage Positive Analog Supply System Ground Device Address Device Address Wiper terminal of the Left Potentiometer Negative terminal of the Left Potentiometer Positive terminal of the Left Potentiometer Wiper terminal of the Right Potentiometer Negative terminal of the Right Potentiometer Positive terminal of the Right Potentiometer Negative Analog Supply FUNCTION
3
FN8203.2 October 17, 2005
X9460 Detailed Pin Description
Host Interface Pins
SERIAL CLOCK (SCL) The SCL input clocks data into and out of the X9460. SERIAL DATA (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wireORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. DEVICE ADDRESS (A1 - A0) The Address inputs are used to set the least significant 2 bits of the 8-bit Slave Byte Address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9460. Up to 4 X9460s may be connected to a single I2C serial bus and written to (NOTE: you cannot read from more than one device on the same 2-wire bus). If left floating, these pins are internally pulled to ground. Slave Byte (bits, MSB-LSB) = 0101 0 A1 A0 R/W The VSS pin is always connected to the system common or ground. VH, VL, VW are the voltages on the RH, RL, and RW potentiometer pins.
X9460 Principles of Operation
The X9460 is a highly integrated microcircuit incorporating two resistor arrays with their associated registers, counters and the serial interface logic providing direct communication between the host and the DCP potentiometers. This section provides detailed description as following: - Resistor Array Description - Serial Interface Description - Command Set and Register Information Description
Resistor Array Description
The X9460 is comprised of two resistor arrays. Each array contains 31 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). Tables 1 and 2 provide a description of the step size and tap positions. At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The five bits of the WCR are decoded to select, and enable, one of thirty-two switches.
TABLE 1. TOTAL -62dB RANGE PLUS MUTE POSITION STEP SIZE -1dB - 2dB - 3dB - 4dB Mute # OF STEPS 11 steps 10 steps 5 steps 4 steps 1 step
Potentiometer Pins
RH-LEFT, RL-LEFT, RH-RIGHT, RL-RIGHT The RH and RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. RW-LEFT, RW-RIGHT The wiper outputs are equivalent to the wiper output of a mechanical potentiometer.
Supply Pins
ANALOG SUPPLY V- AND V+ The positive power supply for the DCP analog control section is connected to V+. The negative power supply for the DCP analog control section is connected to V-. DIGITAL SUPPLIES VCC, VSS The power supplies for the digital control sections.
TABLE 2. WIPER TAP POSITION vs dB TAP POSITION, n for n = 20 to 31 for n = 10 to 19 for n = 5 to 9 for n = 1 to 4 n=0 dB n - 31 2n-51 3n-61 4n-66 -92 MIN/MAX dB -11/0 -31/-13 -46/-34 -62/-50 -92
Power-up and Down Recommendations
There are no restrictions on the power-up condition of VCC, V+ and V- and the voltages applied to the potentiometer pins provided that the VCC and V+ are more positive or equal to the voltage at RH, RL, and RW, ie. VCC, V+ > RH, RL, RW. At all times, the voltages on the potentiometer pins must be less than V+ and more than V-. The following VCC ramp rate spec is always in effect. 0.2 V/ms < VCC ramp < 50 V/ms
4
FN8203.2 October 17, 2005
X9460 Serial Interface Description
Serial Interface
The X9460 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. The X9460 is a slave device in all applications.
Stop Condition
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. The X9460 will respond with an acknowledge: 1) after recognition of a start condition and after an identification and slave address byte, and 2) again after each successful receipt of the instruction or databyte. See Figure 1.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions.
Start Condition
All commands to the X9460 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X9460 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met.
Invalid Commands
For any invalid commands or unrecognizable addresses, the X9460 will NOT acknowledge and return the X9460 to the idle state.
SCL FROM MASTER
1
8
9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER ST AR T ACKNOWLEDGE
FIGURE 1. ACKNOWLEDGE RESPONSE FROM RECEIVER
5
FN8203.2 October 17, 2005
X9460 Command Set and Register Description
Device Addressing
Following a start condition the master must output the Slave Byte Address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 2). For the X9460 this is fixed as 0101.
DEVICE TYPE IDENTIFIER
Several instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9460. These instructions are: Read Wiper Counter Register, Write Wiper Counter Register. The sequence of operations is shown in Figure 4 and 5. The four-byte command is used for write command for both right and left pots (Figure 6).
Special Commands
Increment/Decrement Instruction. The Increment/Decrement command is different from the other commands. Once the command is issued and the X9460 has responded with an acknowledge, the master can clock the selected wiper up and/or down. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 7 and 8 respectively.
0
1
0
1
0
A1
A0
R/W
DEVICE ADDRESS
FIGURE 2. SLAVE BYTE ADDRESS
The next three bits of the Slave Byte Address are the device address. The device address is defined by the A1 - A0 inputs. The X9460 compares the serial data stream with the Slave Byte Address; a successful compare is required for the X9460 to respond with an acknowledge. The A1 - A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. The R/W bit sets the device for read or write operations. Note that the X9460 supports reads and writes to a single device on the 2-wire bus. If more than one X9460 is used on the same 2-wire bus, those devices must have unique device addresses and only writes are supported. You may not read from multiple devices or contention will result and the data is not valid.
Wiper Counter Register
The X9460 contains two Wiper Counter Registers. The Wiper Counter Register output is decoded to select one of thirty-two switches along its resistor array. The Write Wiper Counter Register command directly sets the WCR to a value. The Increment/Decrement instruction steps the register value up or down one to multiple times. The WCR is a volatile register (Table 3) and is reset to the mute position (tap 0, "zero") at power-up.
TABLE 3. WIPER COUNTER REGISTERS, 5-bit - VOLATILE: WCR4 (MSB) WCR3 WCR2 WCR1 WCR0 (LSB)
Command Set
After a Slave Byte Address match, the next byte sent contains the Command and register pointer information. The four most significant bits are the Command. The next bit is a "X" (don't care) set to zero.
this bit not used, set to 0
The X9460 contains one 5-bit Wiper Counter Register for each DCP. (Two 5-bit registers in total.)
I3
I2
I1
I0
0
ZD
RT
LT
INSTRUCTIONS
WIPER COUNTER SELECT
FIGURE 3. COMMAND BYTE FORMAT
The ZD bit enables and disables the Zero Amplitude Wiper Switching circuit. When ZD=1, the wiper switches will turn on when close-to-zero amplitude is detected across the potentiometer pins. When ZD=0, this circuit is disabled. The last two bits, LT (left POT enable) and RT (right POT enable), select which of the two potentiometers is affected by the instruction.
6
FN8203.2 October 17, 2005
X9460
TABLE 4. COMMAND SET INSTRUCTION SET INSTRUCTION Read Wiper I3 I2 I1 I0 X ZD RT LT OPERATION LSB of Slave Byte=1, no command required Slave will return Left then Right Data( not to be used with more than one device on the 2-wire bus) 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 1/0 1/0 1/0 0 1 1 1 0 1 Write new value to the Wiper Counter Register Write new value to the Wiper Counter Register Write new value to the Wiper Counter Register
Write Left Wiper Counter Write Right Wiper Counter Write Both Wiper Counters
Inc/Dec Left Wiper Counter Inc/Dec Right Wiper Counter Inc/Dec Both Wiper Counters Notes: "1/0" = data is one or zero
0 0 0
0 0 0
1 1 1
0 0 0
0 0 0
1/0 1/0 1/0
0 1 1
1 0 1
Enable Increment/decrement of the Control Latch Enable Increment/decrement of the Control Latch Enable Increment/decrement of the Control Latch
SCL
SDA S T A R T 0 1 0 1 0 A1 A0
1 R/W A C K
0 0
0 0
0 0 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 A C K
0 0
0 0
0 0 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 A C K S T O P
DEVICE TYPE IDENTIFIER
LEFT POT DATA BYTE
RIGHT POT DATA BYTE
FIGURE 4. THREE-BYTE COMMAND SEQUENCE (READ, SINGLE DEVICE ON THE 2-WIRE BUS ONLY)
SCL
SDA S T A R T 0 1 0 1 0 A1 A0
0 R/W A C K
1 I3
0 I2
1 I1
0 I0
0 0 ZD RT LT A C K
0 0
0 0
0 0 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 A C K S T O P
DEVICE TYPE IDENTIFIER INSTRUCTION BYTE
RIGHT or LEFT POT DATA BYTE
FIGURE 5. THREE-BYTE COMMAND SEQUENCE (WRITE)
7
FN8203.2 October 17, 2005
X9460
SCL
SDA S01010 T A R DEVICE TYPE T IDENTIFIER
0
1
0
1
0
0
1
1
0 0
0 0
0 W 0C R 4 W C R 3 W C R 2 W C R 1 W CA RC 0K
0 0
0 0
0 W 0C R 4 W C R 3 W C R 2 WW CC RR 10 AS CT KO P
A1 A0 R/W A I3 I2 C K
I1 I0
0 ZD RT LT A C K
LEFT POT INSTRUCTION BYTE DATA BYTE
RIGHT POT DATA BYTE
FIGURE 6. FOUR-BYTE COMMAND SEQUENCE (WRITE)
SCL
SDA S T A R T 0 1 0 1 0 A1 A0
0 R/W A C K
0 I3
0 I2
1 I1
0 I0
0 0 ZD RT LT A C K I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P
DEVICE TYPE IDENTIFIER INSTRUCTION BYTE
INC and DEC ACTIVE
FIGURE 7. INCREMENT/DECREMENT COMMAND SEQUENCE (WRITE)
INC/DEC CMD ISSUED SCL
t WRID
SD A
RW
VOLTAGE OUT
Wiper can move within 10s after the falling edge of SCL
FIGURE 8. INCREMENT/DECREMENT TIMING LIMITS
8
FN8203.2 October 17, 2005
X9460 Instruction Formats
Read Wiper Counter Register (Single device on 2-wire bus only)
device S device type identifier addresses T A R01010AA 10 T Right wiper position M (sent by slave on SDA) A LLLLLC RRRRR 000DDDDD 000DDDDD K 43210 43210 Left wiper position (sent by slave on SDA)
Write Wiper Counter Register
device S device type identifier addresses T A R AA T0101010 Left or Right wiper position S SS A (sent by master on SDA) A T C CO ZRLK DDDDDKP 10100 000 DTT 43210 instruction opcode wiper addresses
R/W=1
S A C K
M A C K
S T O P
Write Both Wiper Counter Registers
device S device type identifier addresses T A R AA 01010 10 T instruction wiper S opcode addresses A C Z K10100 11 D Left wiper position (sent by master on SDA) Right wiper position (sent by master on SDA)
R/W=0
S A C K
Increment/Decrement Wiper Counter Register
S device type identifier T A R0101 T device addresses 0 A1 A0
R/W=0
R/W=0
S A C LLLLL K000DDDDD 43210
S A C RRRRR K 000DDDDD 43210
S A C K
S T O P
instruction wiper S opcode addresses A C 0 0 1 0 0 ZD RT LT K
increment/decrement S (sent by master on SDA) A C I/D I/D . . . . I/D I/D K
S T O P
Definitions: 1. "MACK"/"SACK": stands for the acknowledge sent by the master/slave. 2. "A1 ~ A0": stands for the device addresses sent by the master. 3. "I": stands for the increment operation, SDA held high during active SCL phase (high). 4. "D": stands for the decrement operation, SDA held low during active SCL phase (high).
9
FN8203.2 October 17, 2005
X9460
Absolute Maximum Ratings
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on SDA, SCL or any Address Input with Respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +6V Voltage on V+ (referenced to VSS). . . . . . . . . . . . . . . . . . . . . . . .+6V Voltage on V- (referenced to VSS) . . . . . . . . . . . . . . . . . . . . . . . . -6V (V+) - (V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V Any RH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+ Any RL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300C IW max (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3mA
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40C to 85C X9460V14-2.7 Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V V- Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V to -2.7V V+ Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7V to +5.5V
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Analog Specifications
SYMBOL
Over the recommended operating conditions unless otherwise specified (Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DYNAMIC PERFORMANCE (Notes 2, 3) Control Range Mute Mode SNR THD + N XTalk Signal Noise Ratios (Unweighted) Total Harmonic Distortion + Noise DCP Isolation Digital Feedthrough (Peak Component) -3db Cutoff Frequency DC ACCURACY Step Size Step Size Error Step Size Error Step Size Error Step Size Error DCP to DCP Matching NOTES: 1. VCC = | V- | VCC Ramp up timing 0.2V/ms < Vcc Ramp Rate < 50V/ms 2. This parameter is guaranteed by design and characterization 3. TA = 25oC, VCC = 5.0V; 2 Hz to 20kHz Measurement Bandwidth with 80kHz filter, input signal 1Vrms, 1kHz Sine Wave. Steps of -1, -2, -3, -4 dB For -1dB steps For -2dB steps For -3dB steps For -4dB steps -1 -0.2 -0.4 -0.6 -0.8 -0.1 -4 +0.2 +0.4 +0.6 +0.8 0.1 dB dB dB dB dB dB @1V rms @1V rms @ 1kHz, Tap = -6dB @1V rms @ 1kHz, Tap = -6dB @1kHz, tap = -6dB tap = -6dB -62 -92 -96 -95 -102 -105 100 0 dB dB dB dB dB dB kHz
Analog Specifications
SYMBOL VTERM RTOTAL
Over the recommended operating conditions unless otherwise specified (Note 1) ANALOG INPUTS
PARAMETER Voltage on RL, RW, and RH pins End to End Resistance
TEST CONDITIONS
MIN V-
TYP
MAX V+ +20
UNIT V % pF
Typical 33k TA = 25oC
-20 25 -3
Cin (Note 4) Input Capacitance RL, RH, RW IW (NOte 2) RW VWiper Current Wiper Resistance Voltage on V- pin
+3 100 200 -2.7
mA V
Wiper Current = 3mA -5.5
10
FN8203.2 October 17, 2005
X9460
Analog Specifications
SYMBOL V+ Over the recommended operating conditions unless otherwise specified (Note 1) (Continued) ANALOG INPUTS PARAMETER Voltage on V+ pin Noise TCR (Note 2) Temperature Coefficient of resistance 20Hz to 20kHz, Grounded Input @ -6dB tap TEST CONDITIONS MIN +2.7 2 -300 TYP MAX +5.5 UNIT V Vrms PPM/C
DC Electrical Specifications
SYMBOL ICC1 ISB ILI Iai ILO VIH VIL VOL PARAMETER
Over the recommended operating conditions unless otherwise specified. (Note 1) LIMITS TEST CONDITIONS fSCL = 400kHz, SDA = Open, Other Inputs = VSS SCL = SDA = VCC, Addr. = VSS VIN = VSS to VCC VIN = V- to V+ with all other analog inputs floating VOUT = VSS to VCC VCC x 0.7 -0.5 IOL = 3mA MIN TYP 200 3 1 0.1 10 VCC + 0.5 VCC x 0.1 0.4 10 MAX 300 UNITS A A A A A V V V
VCC Supply Current (Move Wiper, Write, Read) VCC Current (Standby) Input Leakage Current Analog Input Leakage Output Leakage Current Input HIGH Voltage Input LOW Voltage Output LOW Voltage
Capacitance
SYMBOL CI/O (Note 4) CIN (NOte 4) NOTE: 4. This parameter is not 100% tested. TEST Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2 and SCL) TEST CONDITIONS VI/O = 0V VIN = 0V MAX 8 6 UNITS pF pF
11
FN8203.2 October 17, 2005
X9460
A.C. Test Conditions
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5
SDA OUTPUT 100pF 1533
Equivalent A.C. Load Circuit
5V
AC TIMING
SYMBOL fSCL tCYC tHIGH tLOW tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT tR (Note 2) tF (Note 2) tAA (Note 2) tDH (Note 2) TI (Note 2)
Over recommended operating conditions PARAMETER Clock Frequency Clock Cycle Time Clock High Time Clock Low Time Start Setup Time Start Hold Time Stop Setup Time SDA Data Input Setup Time SDA Data Input Hold Time SCL and SDA Rise Time SCL and SDA Fall Time SCL Low to SDA Data Output Valid Time SDA Data Output Hold Time Noise Suppression Time Constant at SCL and SDA inputs 50 50 1300 0 0 2500 600 1300 600 600 600 500 50 300 300 900 MIN MAX 400 UNITS kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tBUF (Note 2) Bus Free Time (Prior to Any Transmission) tSU:WPA tHD:WPA A0, A1 (Note 2) A0, A1 (Note 2)
DC Timing (Note 2)
SYMBOL tWRPO tWRL tWRID PARAMETER Wiper Response Time After The Third (Last) Power Supply Is Stable Wiper Response Time After Instruction Issued (All Load Instructions) Wiper Response Time From An Active SCL Edge (Increment/Decrement Instruction) MIN MAX 10 10 10 UNITS s s s
12
FN8203.2 October 17, 2005
X9460 Timing Diagrams
(START) tR SCL tSU:STA tHD:STA tR SDA tF tSU:STO tF
(STOP)
FIGURE 9. START AND STOP TIMING
tCYC SCL
tHIGH
tLOW SDA tSU:DAT tHD:DAT tBUF
FIGURE 10. INPUT TIMING
SCL
SDA tAA tDH
FIGURE 11. OUTPUT TIMING
(STOP) SCL
SDA
LSB tWRL
VWx
FIGURE 12. DCP TIMING (FOR ALL LOAD INSTRUCTIONS)
13
FN8203.2 October 17, 2005
X9460 Typical Performance Characteristics
(Vcc, V+ = 5.0V, V- = -5.0V, TA = + 25 C, unless otherwise noted)
FFT Spectrum
(with 1kHz 1Vrms input, tap = -6dB)
+0 -1 0 -2 0 -3 0 -4 0 -5 0 -6 0 -7 0 d B V -8 0 -9 0 -1 0 0 -1 1 0 -1 2 0 -1 3 0 -1 4 0 -1 5 0 -1 6 0 -1 7 0 -1 8 0
20 50 100 200 500 1k 2k 5k 10k 20k
Hz
FIGURE 13. SINGLE TONE FREQUENCY RESPONSE
THD+N vs Frequency
(with 80kHz low-pass filter, tap = -6dB)
-6 0 -6 5 -7 0 -7 5 -8 0 -8 5 d B -9 0 -9 5 -1 00 -1 05 -1 10 -1 15 -1 20 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
FIGURE 14. THD + N
14
FN8203.2 October 17, 2005
X9460 Typical Performance Characteristics
(Vcc, V+ = 5.0V, V- = -5.0V, TA = + 25 C, unless otherwise noted)
Mut e Mod e
+0 -10 -20 -30 -40 -50 -60 d B V -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
FIGURE 15. MUTE
15
FN8203.2 October 17, 2005
X9460 Packaging Information
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.193 (4.9) .200 (5.1)
.047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05) See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
FN8203.2 October 17, 2005

▲Up To Search▲

Price & Availability of X9460KV14I

	To Download X9460KV14I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .